This invention relates generally to decoder circuits having a large number of inputs, for example, the decoder used in redundancy circuits and more particularly, it relates to a BICMOS (bipolar/CMOS mixed type) decoder circuit which maintains a high noise margin and a low pattern sensitivity even with a large number of inputs.
Conventional decoder circuits employing only MOS (metal-oxide semiconductor) transistors are generally well known in the prior art. When such prior art decoder circuits are used, for example, in redundancy type circuits, there is required a relatively large number of inputs. As a result, these prior art decoder circuits suffer from the disadvantage of reduced noise margin and high pattern sensitivity when the number of decoder inputs increases.
It would therefore be desirable to provide a merged or composite bipolar/CMOS decoder circuit which has the advantages of high noise margin and low pattern sensitivity. The decoder circuit of the present invention is achieved by combining the bipolar transistor and CMOS transistor technologies together. As a result, bipolar transistors and CMOS transistors are merged or are arranged in a common semiconductor substrate in order to form an integrated circuit decoder device of the present invention.